[ILUG] [ getting OT] SMP & powersaving - java on a sparc

[Shane Dempsey]

Ah , its all clear now.
Any chance of the next INTEL processors being more
SMP friendly ? Seems a shame to make the same mistakes
again and again ...

Also could anyone confirm / refute that the latest SPARCs
have circuits which act like JVM's ( not fully but enough that bytecode on
a SPARC is going to be close to native code)  I read this somewhere but I
just
can't remember the source.

BTW xena ?   >:-))

    ...shane

----- Original Message -----
From: John P. Looney <jplooney-ilug at online.ie>
To: <ilug at linux.ie>
Sent: 07 January 2000 08:53
Subject: Re: [ILUG] SMP & powersaving
>
>  I thought they re-wrote the book for SMP systems on Intel. That's why it
> rocks so much :)
>
> xena [0]  cat /proc/interrupts
>            CPU0       CPU1
>   0:    4186169    4160816    IO-APIC-edge  timer
>   1:      72686      72444    IO-APIC-edge  keyboard
>   2:          0          0          XT-PIC  cascade
>   9:          0          0    IO-APIC-edge  acpi
>  12:     460479     460847    IO-APIC-edge  PS/2 Mouse
>  13:          1          0          XT-PIC  fpu
>  15:      83377      82605    IO-APIC-edge  ide1
>  16:     462957     464316   IO-APIC-level  es1371
>  18:     531573     531831   IO-APIC-level  ide2, eth0
> NMI:    8346927    8346927
> LOC:    8345909    8345910
> ERR:          1
>
>  Kick ass. Loads of interrupts, and loads of space!